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Accellera Systems Initiative Releases UVM 1.2

"The UVM working group has achieved the goals of its charter to enhance SoC productivity throughout the industry," said Tom Alsop, UVM Working Group co-chair. "We are proud to report that UVM 1.2 continues the work to define new features and improve quality of the reference implementation."

Messaging, sequences, register layer and other features enhanced in successful standard

Napa, Calif., USA, 24 June 2014 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced it released a new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. The ... More »

Latest Accellera Systems Initiative Press Releases
Accellera Systems Initiative Releases UVM 1.2 24 Jun 2014
Accellera Systems Initiative Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard 03 Jun 2014
Synopsys' Yatin Trivedi to Receive 2014 Accellera Leadership Award 29 May 2014
Accellera Systems Initiative advances the SystemC ecosystem with the release of the core language and verification libraries 24 Apr 2014
Andy Goodrich Receives Accellera Systems Initiative Technical Excellence Award 03 Mar 2014
EDA and IP Standards Highlight Accellera Day, March 3 at 2014 Design and Verification Conference and Exhibition 13 Feb 2014
Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development 15 Oct 2013
Accellera Systems Initiative Enhances IP-XACT Standard with New Vendor Extensions for Analog/Mixed-Signal and Low-Power Designs 30 Sep 2013

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Latest Member Press Releases
European Project "VERDI" provides Universal Verification Methodology (UVM) in SystemC to Accellera Systems Initiative as new industry standard proposal 02 Jun 2014
Agnisys, Inc. joins Accellera Systems Initiative 06 Aug 2013
STMicroelectronics, ARM and Cadence Improve Tool and Model Interoperability with Three Joint Contributions to Accellera Systems Initiative 29 Jul 2013
Virtual Platform - Quick Start Package (VP-QSP) from CircuitSutra 01 May 2013
Mentor Graphics Verification Academy Launches Coverage Cookbook 19 Nov 2012
Synopsys Honors Accellera Systems Initiative with 2012 Tenzing Norgay Interoperability Achievement Award 24 May 2012
Mentor Graphics Drives Broader Adoption of UVM 22 Feb 2012
ASTC joins Accellera Systems Initiative 28 Dec 2011

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Latest Media Coverage
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Intel's Shishpal Rawat: Multiple hats, Singular focus

Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that's accurate. Rawat is so busy these days, it's hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.

25 Sep 2014
Accellera Updates UVM Standard

New verification standard readied for submission to IEEE; 90-day public comment period begins.

Semiconductor Engineering
01 Jul 2014
Accellera Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard

Accellera announces it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs in which the effects of, and interactions among, different disciplines such as electrical, mechanical, fluid dynamics and thermal are important.

Low-Power Design
03 Jun 2014
Accellera publishes SystemC-AMS 2.0 standard

Accellera Systems Initiative has published the language reference manual for the latest version of its mixed-signal simulation environment based on SystemC. Version 2.0 of SystemC-AMS adds support for more dynamic behaviors in the analog domain.

Tech Design Forum
20 Mar 2013
DVCon 2013: Engineers Question EDA Standards Leaders at Accellera "Town Hall" Meeting

Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers.

Cadence Industry Insights Blog
25 Feb 2013
Master & Commander: DVCon's Stan Krolikoski

Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it's about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It's also the amount of time Stan's been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.

06 Feb 2013

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