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7th Symposium on Electronic System-Level Design with SystemC

Free to industry professionals!
June 8, 4:00pm - 7:00pm
June 9, 12:00pm - 5:00pm

Register Now!

ESL technologies continue to grow in importance for architectural exploration, performance analysis, the building of virtual platforms for software development and functional verification. The development of standards such as IEEE 1666, SystemC and the OSCI transaction-level modeling standard, TLM-2.0, mark significant milestones in enabling standards-based solutions.

Now in its 7th year, the Symposium on Electronic System-Level Design with SystemC provides an open forum for SystemC users, tool suppliers, and academia to interact and learn about the latest advances in system-level design with SystemC. Sponsored by the Open SystemC Initiative, the symposium features presentations from users and industry experts who discuss SystemC design methodology and real-world user experiences.

Co-located with Design Automation Conference (DAC) 2008.

Opening Session and Reception – North American SystemC Users Group Meeting

Sunday, June 8, 4:00pm - 7:00pm
Hilton Anaheim Hotel, 777 Convention Way, Ballroom A

NASCUG provides a unique forum for sharing SystemC experiences among business, research and universities, while influencing the growth and evolution of SystemC standards. The meeting includes technical presentations on the OSCI TLM-2.0 standard, SystemC and analog/mixed-signal design, and SystemC tool flows and methodologies.

View the meeting agenda.

Panel Discussion: Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse

Monday, June 9, 12:00pm - 2:00pm
Ballroom E, Anaheim Convention Center
Complimentary lunch provided; doors open at 11:30am

Moderated by Ron Wilson, Executive Editor, EDN

This informative lunch panel brings together a unique combination of thought leaders in electronic systems, software, and semiconductors for a lively discussion on the economic impact of ESL, SystemC and transaction-level modeling (TLM). Find out why the release of the OSCI TLM-2.0 standard is important to them and how their organization is using it today to increase design success and improve productivity. You’ll also hear their predictions on the future of TLM-2.0 and how it can create new value by enabling significantly earlier architecture definition and software development for SoC designs.

Panelists include:

  • Ken Tallo, Director of Virtual Platforms, SoC Enabling Group, Intel
  • Tauseef Kazi, Principal Engineer, Qualcomm
  • Prakash Rashinkar, Director of Engineering, Rambus

Special Workshop: OSCI TLM-2.0 in 2008 – A Leap Forward for Transaction-Level Modeling Standards

Monday, June 9, 2:00pm - 5:00pm
Ballroom E, Anaheim Convention Center

This workshop presents details of the finalized OSCI TLM-2.0 standard. This standard marks the culmination of several years of intensive work by the OSCI TLM Working Group. TLM-2.0 explicitly addresses the interoperability of memory-mapped bus models at the transaction level and provides a foundation and framework for the transaction-level modeling of other protocols. Robust examples and documentation will be presented. Attendees will be provided with a comprehensive workshop guide containing course materials.

Thank you to our sponsors: