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Media Coverage
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ESL - where we're at and where we're going

Gary Smith of GarySmithEDA presented a snapshot of the status and direction of electronic system level design (ESL) methodology at the recent Open SystemC Initiative (OSCI) SystemC day at the Design and Verification Conference (DVCon 2010) in San Jose, California. He talked about the progress of ESL, its five high value applications, market sizing and concluded with some comments about its ability to satisfy the needs of the embedded system software developer.

SCDsource
09 Mar 2010
Open SystemC Initiative releases analog/mixed-signal extensions standard

AMS 1.0 offers three different formalisms for modeling AMS blocks: Electrical Linear Networks (ELN), Linear Signal Flow (LSF), and Timed Data Flow (TDF). The first method, ELN, is what the working group calls a "conservative" model: that is, such models use differential equations that preserve Kirkhoff's Laws at a node level...

EDN
08 Mar 2010
Consortium to develop smart local grid management SoC/SiP and infrastructure concept

The planned deliverables include...A toolkit for modeling and analyzing smart energy grids at various levels of abstraction, written in SystemC, a C++ class library. This includes functional models of a local energy grid consisting of energy-consuming units and a decentralized wind turbine...

SCDsource
08 Mar 2010
OSCI Completes First Analog/Mixed-Signal Standard

Designed for use with IEEE Std. 1666-2005, the AMS language standardizes new class libraries, layered on top of the SystemC standard, featuring specialized AMS system-level design and modeling methods. The AMS language reference manual (LRM) introduces new execution semantics for efficient simulation of discrete- and continuous-time behavior, and incorporates updates from the public review conducted in early 2009...

Gabe on EDA
08 Mar 2010
Irrational Exuberance Meets High-Level Design

Irrational exuberance is running rampant. Design managers believe all their systems engineers and software programmers are going to be able to drive the hardware design process from a high-level description.

Chip DesignJon McDonald Blog
25 Feb 2010
DVCon SystemC Day Quandry: Need for Third Party TLM IP

Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was only a small amount of discussion about the need for third-party transaction level modeling (TLM) IP.

Richard Goering Blog/Cadence Community Post
24 Feb 2010
DVCon SystemC Day - Forging A TLM Design/Verification Flow

TLM-driven design and verification will occur in a "multi-abstraction" environment. The best approach is to start from the top with algorithm design and verification, go through the loop to complete that process, and move down to architectural verification, while reusing as much from the algorithmic level as possible. The next step is to move from architectural to micro-architectural verification, again reusing as much as possible.

Cadence Industry Insights Blog
23 Feb 2010
SystemC configuration spec ready for review

The Open SystemC Initiative (OSCI) has released a draft of requirements for the configuration portion of the SystemC Configuration, Control & Inspection (CCI) standardization effort. It is open for public review until April 2, 2010.

EE Times
23 Feb 2010
TLM Enabled A True Paradigm Shift

Yesterday I spent some time with Eric Lish, the Chair of OSCI. Eric is an Intel veteran, having spent 21 years, and counting, with "the other big blue" company. At present he manages the Virtual Platform Center of Excellence in Chandler Arizona. In discussing OSCI's past achievements and future plans it became clear to me that if one had to identify the single most important contribution the consortium has made to EDA, one would have to choose TLM. Transaction Level Modeling was not a new concept before OSCI turned its attention to it. VHDL, in fact, the greatly misunderstood and poorly marketed language, can in fact be used for architectural exploration and modeling at the transaction level.

Gabe on EDA
23 Feb 2010
TLM Enabled A True Paradigm Shift

In discussing OSCI's past achievements and future plans it became clear to me that if one had to identify the single most important contribution the consortium has made to EDA, one would have to choose TLM...

Gabe on EDA
23 Feb 2010
Need another reason to use SystemC for HLS? The verification advantage is the best of all.

The "language war" in high-level system (HLS) design has been waging for a while now. You've probably read a lot of online publications touting the advantages of using SystemC over ANSI C to design at an abstract level. If you were to take what everyone is saying and boil it down to a few key points, they might sound something like this...

Forte Cyn City Blog
22 Feb 2010
Open SystemC Initiative Announces Public Review for CCI Standardization Effort

he goal of the public review of the Configuration Requirements Specification is to gather useful feedback to prepare for the creation of a draft standard to allow models to incorporate configuration parameters, allowing any tool to connect and perform the required configuration. Configuration will be used to specify a system's initial setup, orchestrate run-time operation, control system analyses and many other purposes.

Gabe on EDA
22 Feb 2010
High-level synthesis, verification and language

Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.

EDA DesignLine
22 Feb 2010
Q&A: How System Design And Verification Can Go "Mainstream"

One of the paradigm shifts we see is that more and more semiconductor and IP companies are delivering the hardware together with the software to the system integrator. An IP company needs to think about all the different configurations in which the software will interact with the hardware and create regression tests to test those scenarios.

Cadence Industry Insights Blog
18 Feb 2010
Mentor adds SystemC support to Catapult C

Mentor Graphics has continued to expand the reach of its product with its core Catapult C synthesis engine. In December, the company added support for control-logic synthesis and some level of power management. The company has now taken another step, adding a preprocessor that makes SystemC code into a form that the Catapult C engine can use.

EDN
18 Feb 2010
Design Verification Experts to Meet at DVCon

Next week, specifically February 22 to 25, is a special time for those who have the responsibility to verify electronics designs or to develop tools to enable or improve such verification. DVCon, the annual conference dedicated to design verification will be held at the DoubleTree hotel in San Jose.

Gabe on EDA
17 Feb 2010
The Hitchhiker's Guide to ESL - Part 2 - Abstraction and Automation

In part 2 of the Hitchhiker's guide to system-level design we will look at development abstraction levels and required productivity improvements to keep up with the fast pace of complexity growth. In the first part of this guide we had reviewed this complexity growth from 29,000 transistors in 1979 to 2 billion 30 years later.

Frank Schirrmeister Blog/Synopsys Community Post
17 Feb 2010
Is HLS finally converging on a standard language?

The arrival of a new decade has brought with it a change in the electronic system level (ESL) landscape. We've seen some new developments and interesting changes. Hardware developers who have decided to create their next design with a high-level synthesis (HLS) tool have yet another critical decision to make: which language to use.

SCDSource
16 Feb 2010
Virtual Consolidation

It has now been more than a week - time for the dust to settle a little bit, on the news from two weeks ago and last week that Synopsys had acquired VaST, and then CoWare; and that Intel had acquired Virtutech and was planning to merge it into its Wind River subsidiary.

Grant Martin Blog/Chip Design Magazine
15 Feb 2010
SystemC Day at DVCon

The Open SystemC Initiative (OSCI)... announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.

Mentor Verification Horizons Blog
10 Feb 2010

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