Media Coverage

Cadence last week announced the publication of a new book entitled TLM-Driven Design and Verification Methodology. Available on-line, the book describes in very practical terms what's needed to implement a transaction-level modeling (TLM) based design and verification flow. In this roundtable interview, four Cadence co-authors - Michael McNamara, Guy Mosenson, Mike Stellfox, and Yosinori Watanabe - join with another co-author, consultant Brian Bailey, to answer questions related to the book and its contents.

SystemC Japan 2010, Friday, July 2. This one-day industry event will feature technical presentations on the use of SystemC for system-level design from industry experts and suppliers, highlighted by user case studies. The agenda features six technical user presentations by top Japanese electronics companies and four informative presentations from leading suppliers of electronic design automation tools and technologies.

It's far easier to do architecture design in SystemC than it is to do it in C and C++. If co-designing hardware and software using high-level design methods, much of your work will be done in an architecture design phase in SystemC. Here's why.

The Open SystemC Initiative, the industry association that has shepherded various standards initiatives involving the SystemC language, is on the move again and has recently released its SystemC Analog/Mixed-Signal (AMS) extensions language standard. The AMS 1.0 standard is the first modeling language targeting system-level design and verification to describe analog/mixed-signal behavior as a natural extension to existing SystemC-based design methodologies.

If there is a hierarchy of techie-ness, analog designers come pretty high-up in the hierarchy. Where digital IC design teams have moved from drawing polygons, through schematic entry to RTL, and are now grappling with ESL tools, the analog guys continue to draw polygons. And analog design is hard: it takes a long time to learn to do, and requires a special mind-set to do it well. This has always been a problem and it is becoming an even more serious problem as analog moves from being a niche activity to something that, if not centre stage, is certainly playing a major supporting role in many devices. Where analog used to be confined to its own chip, SoCs and ASICs are adding areas of analog and mixed signal for greatly increased functionality.

AMS 1.0 offers three different formalisms for modeling AMS blocks: Electrical Linear Networks (ELN), Linear Signal Flow (LSF), and Timed Data Flow (TDF). The first method, ELN, is what the working group calls a "conservative" model: that is, such models use differential equations that preserve Kirkhoff's Laws at a node level...

Designed for use with IEEE Std. 1666-2005, the AMS language standardizes new class libraries, layered on top of the SystemC standard, featuring specialized AMS system-level design and modeling methods. The AMS language reference manual (LRM) introduces new execution semantics for efficient simulation of discrete- and continuous-time behavior, and incorporates updates from the public review conducted in early 2009...

Irrational exuberance is running rampant. Design managers believe all their systems engineers and software programmers are going to be able to drive the hardware design process from a high-level description.

TLM-driven design and verification will occur in a "multi-abstraction" environment. The best approach is to start from the top with algorithm design and verification, go through the loop to complete that process, and move down to architectural verification, while reusing as much from the algorithmic level as possible. The next step is to move from architectural to micro-architectural verification, again reusing as much as possible.

Yesterday I spent some time with Eric Lish, the Chair of OSCI. Eric is an Intel veteran, having spent 21 years, and counting, with "the other big blue" company. At present he manages the Virtual Platform Center of Excellence in Chandler Arizona. In discussing OSCI's past achievements and future plans it became clear to me that if one had to identify the single most important contribution the consortium has made to EDA, one would have to choose TLM. Transaction Level Modeling was not a new concept before OSCI turned its attention to it. VHDL, in fact, the greatly misunderstood and poorly marketed language, can in fact be used for architectural exploration and modeling at the transaction level.