Media Coverage

Gary Smith of GarySmithEDA presented a snapshot of the status and direction of electronic system level design (ESL) methodology at the recent Open SystemC Initiative (OSCI) SystemC day at the Design and Verification Conference (DVCon 2010) in San Jose, California. He talked about the progress of ESL, its five high value applications, market sizing and concluded with some comments about its ability to satisfy the needs of the embedded system software developer.

The planned deliverables include...A toolkit for modeling and analyzing smart energy grids at various levels of abstraction, written in SystemC, a C++ class library. This includes functional models of a local energy grid consisting of energy-consuming units and a decentralized wind turbine...

Irrational exuberance is running rampant. Design managers believe all their systems engineers and software programmers are going to be able to drive the hardware design process from a high-level description.

TLM-driven design and verification will occur in a "multi-abstraction" environment. The best approach is to start from the top with algorithm design and verification, go through the loop to complete that process, and move down to architectural verification, while reusing as much from the algorithmic level as possible. The next step is to move from architectural to micro-architectural verification, again reusing as much as possible.

Yesterday I spent some time with Eric Lish, the Chair of OSCI. Eric is an Intel veteran, having spent 21 years, and counting, with "the other big blue" company. At present he manages the Virtual Platform Center of Excellence in Chandler Arizona. In discussing OSCI's past achievements and future plans it became clear to me that if one had to identify the single most important contribution the consortium has made to EDA, one would have to choose TLM. Transaction Level Modeling was not a new concept before OSCI turned its attention to it. VHDL, in fact, the greatly misunderstood and poorly marketed language, can in fact be used for architectural exploration and modeling at the transaction level.

The "language war" in high-level system (HLS) design has been waging for a while now. You've probably read a lot of online publications touting the advantages of using SystemC over ANSI C to design at an abstract level. If you were to take what everyone is saying and boil it down to a few key points, they might sound something like this...

Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.

Mentor Graphics has continued to expand the reach of its product with its core Catapult C synthesis engine. In December, the company added support for control-logic synthesis and some level of power management. The company has now taken another step, adding a preprocessor that makes SystemC code into a form that the Catapult C engine can use.

In part 2 of the Hitchhiker's guide to system-level design we will look at development abstraction levels and required productivity improvements to keep up with the fast pace of complexity growth. In the first part of this guide we had reviewed this complexity growth from 29,000 transistors in 1979 to 2 billion 30 years later.

It has now been more than a week - time for the dust to settle a little bit, on the news from two weeks ago and last week that Synopsys had acquired VaST, and then CoWare; and that Intel had acquired Virtutech and was planning to merge it into its Wind River subsidiary.