Media Coverage
If you have seen a relevant article not listed below, please let us know.
| Media Coverage | |
| Links will open in a new window. | |
| Need another reason to use SystemC for HLS? The verification advantage is the best of all.
The "language war" in high-level system (HLS) design has been waging for a while now. You've probably read a lot of online publications touting the advantages of using SystemC over ANSI C to design at an abstract level. If you were to take what everyone is saying and boil it down to a few key points, they might sound something like this... |
Forte Cyn City Blog 22 Feb 2010 |
| Open SystemC Initiative Announces Public Review for CCI Standardization Effort
he goal of the public review of the Configuration Requirements Specification is to gather useful feedback to prepare for the creation of a draft standard to allow models to incorporate configuration parameters, allowing any tool to connect and perform the required configuration. Configuration will be used to specify a system's initial setup, orchestrate run-time operation, control system analyses and many other purposes. |
Gabe on EDA 22 Feb 2010 |
| High-level synthesis, verification and language
Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way. |
EDA DesignLine 22 Feb 2010 |
| Q&A: How System Design And Verification Can Go "Mainstream"
One of the paradigm shifts we see is that more and more semiconductor and IP companies are delivering the hardware together with the software to the system integrator. An IP company needs to think about all the different configurations in which the software will interact with the hardware and create regression tests to test those scenarios. |
Cadence Industry Insights Blog 18 Feb 2010 |
| Mentor adds SystemC support to Catapult C
Mentor Graphics has continued to expand the reach of its product with its core Catapult C synthesis engine. In December, the company added support for control-logic synthesis and some level of power management. The company has now taken another step, adding a preprocessor that makes SystemC code into a form that the Catapult C engine can use. |
EDN 18 Feb 2010 |
| Design Verification Experts to Meet at DVCon
Next week, specifically February 22 to 25, is a special time for those who have the responsibility to verify electronics designs or to develop tools to enable or improve such verification. DVCon, the annual conference dedicated to design verification will be held at the DoubleTree hotel in San Jose. |
Gabe on EDA 17 Feb 2010 |
| The Hitchhiker's Guide to ESL - Part 2 - Abstraction and Automation
In part 2 of the Hitchhiker's guide to system-level design we will look at development abstraction levels and required productivity improvements to keep up with the fast pace of complexity growth. In the first part of this guide we had reviewed this complexity growth from 29,000 transistors in 1979 to 2 billion 30 years later. |
Frank Schirrmeister Blog/Synopsys Community Post 17 Feb 2010 |
| Is HLS finally converging on a standard language?
The arrival of a new decade has brought with it a change in the electronic system level (ESL) landscape. We've seen some new developments and interesting changes. Hardware developers who have decided to create their next design with a high-level synthesis (HLS) tool have yet another critical decision to make: which language to use. |
SCDSource 16 Feb 2010 |
| Virtual Consolidation
It has now been more than a week - time for the dust to settle a little bit, on the news from two weeks ago and last week that Synopsys had acquired VaST, and then CoWare; and that Intel had acquired Virtutech and was planning to merge it into its Wind River subsidiary. |
Grant Martin Blog/Chip Design Magazine 15 Feb 2010 |
| SystemC Day at DVCon
The Open SystemC Initiative (OSCI)... announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22. |
Mentor Verification Horizons Blog 10 Feb 2010 |
| Carpentry Lessons Applied To ESL
Electronic system level design and analysis. How many tools fall under this general description? How many languages are applied in the various stages of system design and analysis? |
Chip Design 28 Jan 2010 |
| OCP-IP Kit Delivers OSCI TLM 2.0 Compatibility
Open Core Protocol International Partnership (OCP-IP) today announced the availability of version 2.2x2.1 of the OCP Modeling Kit. The new version is compatible with OSCI's TLM 2.0.1, the most recent version of TLM 2. |
Chip Design 27 Jan 2010 |
| CoFluent Studio generates SystemC models for Mentor's Questa
CoFluent Design said its CoFluent Studio ESL modeling and simulation software environment automatically generates SystemC models and test cases for Mentor Graphics' Questa functional verification platform. |
EE Times 26 Jan 2010 |
| SystemC Mixed-HDL IP Reuse Methodology
There is an urgent need to have an efficient SystemC-HDL cross-language methodology that breaks the language barriers and tightly integrates the different standards as one. This methodology will help designers reduce their verification process by using verification IP that is developed using a rich set of verification features and methodologies across multiple languages. |
Design and Reuse 26 Jan 2010 |
| Bridging ESL and High-Level Synthesis
As the market for high-level synthesis becomes more crowded - conveniently timed to coincide with the rising complexity at advanced process nodes - vendors have begun pushing the tools to do far more than ever before. |
Chip Design 25 Jan 2010 |
| Driving the Transition to the System-Level
For years, the EDA industry has waited for Electronic System-Level (ESL) design to find broader adoption. Probably the most significant change needed for this transition to occur is a move to higher levels of abstraction, at some level above the current entry-level referred to as Register Transfer Level (RTL). |
Gabe on EDA 25 Jan 2010 |
| DesignWare supports SuperSpeed USB 3.0
Supporting the Open SystemC Initiative (OSCI) TLM-2.0 API specification, the SuperSpeed USB 3.0 models are part of the DesignWare System-Level Library which features more than 100 TLM models, including models of the DesignWare Interface IP portfolio. |
EE Times 12 Jan 2010 |
| Open SystemC Initiative Commemorates 10-Year Anniversary
Introduced at the 1999 Embedded Systems Conference and "setting the stage for what could be a new era in electronics design," according to EE Times, a group of 35 EDA companies formed a coalition to create an "open-source C++ 'modeling platform' to allow hardware, software and systems design in C or C++." |
Gabe on EDA 14 Dec 2009 |
| SystemC, Ten Years Later...
10 years. It's almost hard to believe, but it has already been a decade since the birth of OSCI. The Open SystemC Initiative was officially launched in September of 1999. A few months later, SystemC v0.91 was released. I remember my genuine curiosity when I downloaded the source files and built that first version of the simulator... |
Electronic System Level Design Blog 19 Nov 2009 |
| SystemC synthesis subset draft standard released
OSCI is calling on SystemC users and developers to participate in the public review of the Synthesis subset draft 1.3 standard. Results of the review and comments are expected to be made public in the third quarter of 2010. |
EDA DesignLine 09 Nov 2009 |
<< Previous Results | Next Results >>