SystemC Day 2010 Video Presentations

Gary Smith, Gary Smith EDA, USA

EDA Analyst Gary Smith discusses the long, strange trip of ESL and makes predictions about where the technology and market are headed.

The Metaport: A Technique for Managing Code Complexity
Jack Donovan, HighIP Design, Texas, USA

The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation.
 

OCP Socket Modeling with TLM-2.0
Hervé Alexanian, Sonics Inc., California, USA

This presentation discusses work performed by the OCP-IP Committee. It introduces a modeling kit based on the TLM-2.0 standard to represent OCP data transfers and covers use models on a spectrum ranging from loosely timed to cycle accurate.
 

ADL Synthesis using ArchC
Samuel Goto, Master student at UNICAMP

The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level.
 

Look Ma, No Clocks! Improving Model Performance
David Black, XtremeEDA, Texas, USA

This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed.
 

TLM-driven Design and Verification Methodology
Brian Bailey, independent consultant

SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature.
 

OSCI Technical WG Update
Eric Lish, OSCI Chairman

The OSCI Technical Working Group update can be viewed with the other videos or separately without  registration. View now >>